1. Field of the Invention
The present invention relates to a three-dimensional type semiconductor device and a method of producing the same, and more particularly, it relates to a three-dimensional type semiconductor device having a reduced distance of an interlayer interconnection, and a method of producing the same.
2. Description of the Prior Art
A three dimensional circuit having a reduced distance between semiconductor devices has been achieved as a three-dimensional type semiconductor device in these days. Such a three-dimensional circuit is disclosed in an article by H. Shichijo et al., entitled "POLYSILICON TRANSISTORS IN VLSI MOS MEMORIES", IEDM, SESSION 9.1, 1984, pp. 228-231.
FIG. 1 is a cross sectional view showing an example of a conventional three-dimensional type semiconductor device.
Referring now to FIG. 1, the structure of a conventional three-dimensional type semiconductor device is described.
In FIG. 1, an insulating layer 3 is formed on a first semiconductor integrated circuit layer 1 (referred to as a first layer), and a second semiconductor integrated circuit layer 2 (referred to as a second layer) is formed on the insulating layer 3.
More specifically, the first layer comprises active regions 12, insulating layers 13 and interconnection layers 11 for interconnecting the active regions 12 to each other. Each semiconductor elemental device comprises an MOS (Metal Oxide Semiconductor) transistor having a gate electrode 14. In addition, the second layer comprises active regions 22, insulating layers 23 and interconnection layers 21 for interconnecting the active regions 22 to each other. Each semiconductor elemental device comprises an MOS transistor having a gate electrode 24. The first and second layers are electrically connected to each other through a through-hole 4.
According to the conventional three-dimensional type semiconductor device shown in FIG. 1, in order to electrically couple the semiconductor elemental device included in the first layer to the semiconductor elemental device included in the second layer, an interlayer interconnection through the through-hole 4 must be utilized. For example, in FIG. 1, in order to electrically connect an active region 22b in the semiconductor elemental device included in the second layer to an active region 12b in the semiconductor elemental device included in the first layer, which is located immediately under the active region 22b, the through-hole 4 was provided laterally apart from the active regions in the semiconductor elemental devices and an interlayer interconnection through the through-hole 4 was applied. Thus, a distance of an interconnection for connecting semiconductor elemental devices in different layers was increased, so that a short distance between devices, which is one of the characteristics of the three-dimensional circuit, could not be made use of. More specifically, when the distance of an interconnection is thus increased, resistance and capacitance of interconnection could not be neglected, depending on materials for interconnection. Furthermore, since the through-hole is provided in a separate position apart from the semiconductor elemental devices, the conventional semiconductor device shown in FIG. 1 was very disadvantageous from the viewpoint of improvement of integration.